Effect of boundary roughness on the variability of the I-V data of silicon field-effect GAA nanotransistors

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Abstract

The influence of various sources of variability on transistor performance increases with the transition to three-dimensional architectures, and the roughness boundary of the transistor's working area is one of the main factors contributing to this increase. In this paper, the variability of the key parameters of silicon field-effect GAA nanotransistors with an unalloyed cylindrical working area with different working area lengths from 25 to 10 nm is investigated to demonstrate the effect of scaling. Fluctuations in the characteristics are analyzed for two values of correlation lengths of 10 nm and 20 nm and a range of RMS values of boundary deviations in the range from 0.4 to 0.85 nm. For the key parameters under study, threshold voltage, Ion and Ioff currents, the standard deviation values for transistor structures with different channel lengths differ by about 2 times. At the same time, the patterns of variability of key parameters are functionally different. The consequence of this is that the methods for optimizing the effect of variability are not scalable due to the effect of boundary roughness.

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About the authors

N. V. Masalsky

Kurchatov Institute

Author for correspondence.
Email: volkov@niisi.ras.ru
Russian Federation, Moscow

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Supplementary files

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2. Fig. 1. Schematics of the variation of the working area of the GAA field-effect nanotransistor due to the LER mechanism. The initial shape of the working region is reflected by the grey rectangle behind the figures. 1 - source, 2 - drain, 3 - working region, Lg - length of the working region

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3. Fig. 2. Dependence of σ (Uth) on ∆ at Λ = 20 nm and 10 nm, where the two lower ones are Lg = 25 nm and the two upper ones Lg = 10.2 nm. In both families, the upper curve is Λ = 20 nm and the lower curve is Λ = 10 nm at Uds = 0.05 V in all cases

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4. Fig. 3. Dependence of σUth / Lg on ∆ at Uds = 0.05 V and Λ = 20 nm, where 1 - Lg = 25 nm, 2 - Lg = 10.2 nm

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5. Fig. 4. Dependence of the correlation coefficient (CC) of threshold voltages at high drain bias versus threshold voltages at low drain bias on ∆, where 1 - Lg = 25 nm and Λ = 20 nm, 2 - Lg = 25 nm and Λ = 10 nm, 3 - Lg = 10.2 nm and Λ = 20 nm, 4 - Lg = 10.2 and Λ = 10 nm. The inset shows the scattering diagram of Uth at different Uds

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6. Fig. 5. Dependence of σ (log(Ioff)) on ∆ at Λ = 20 nm and 10 nm, where the lower two are Lg = 25 nm and the upper two Lg = 10.2 nm. In both families, the upper curve is Λ = 20 nm and the lower curve is Λ = 10 nm

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7. Fig. 6. Dependence of the standard deviation of the Ion current (σIon (μA/μm) on ∆ (nm) for transistors Lg = 10.2 nm (top two) and 25 nm (bottom two) and Λ = 20 (top in both groups) and 10 nm (bottom in both groups)

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8. Fig. 7. Spatial sensitivity of the Ioff current of the two prototypes to the type of strain in width, and with offset, at low and high voltage Uds. 1 - Lg = 25 nm, warp, Uds = 10 mV; 2 - Lg = 25 nm, thickening, Uds = 10 mV; 3 - Lg = 25 nm, warp, Uds = 1.0 V; 4 - Lg = 25 nm, thickening, Uds = 1.0 V; 5 - Lg = 10 nm, warp, Uds = 0.6 V; 6 - Lg = 10 nm, thickening, Uds = 0.6 V

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9. Fig. 8. Spatial sensitivity of the Ion current of the two prototypes to strain type in width, and with offset, where 1 - Lg = 25 nm, thickening; 2 - Lg = 25 nm, curvature; 3 - Lg = 10 nm, thickening; 4 - Lg = 10 nm, curvature

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